Fast TCP/IP stack in hardware

The hwIP stack is written in about 1100 lines of Mobius and supports ARP, ICMP, UDP and TCP. The entire stack is implemented as 100% hardware for maximum throughput and minimum latency.

• The Iperf application reports 990 Mbps for TCP throughput using jumbo packets over a 1 Gbps direct connection.
• The Wireshark application reports latencies of 2 microseconds for standard sized packets over a 1 Gbps direct connection.

The hwIP logic is connected to a Xilinx coregenerator MAC (e.g. 1000/100/10 Mbps TEMAC) via a locallink-fifo. The hwIP is configurable to provide only the functionality required for the user's application. On a Xilinx Virtex5 the hwIP occupies about 4000 slices (ARP, ICMP, UDP) or 9000 slices (ARP, ICMP, UDP, TCP). Application notes are being written that discuss its operation, testing and performance.