Fast TCP/IP stack in hardware

The hwIP stack is written in about 1100 lines of Mobius and supports ARP, ICMP, UDP and TCP. The entire stack is implemented as 100% hardware for maximum throughput and minimum latency.

• The Iperf application reports 990 Mbps for TCP throughput using jumbo packets over a 1 Gbps direct connection.
• The Wireshark application reports latencies of 2 microseconds for standard sized packets over a 1 Gbps direct connection.

The hwIP logic is connected to a Xilinx coregenerator MAC (e.g. 1000/100/10 Mbps TEMAC) via a locallink-fifo. The hwIP is configurable to provide only the functionality required for the user's application. On a Xilinx Virtex5 the hwIP occupies about 4000 slices (ARP, ICMP, UDP) or 9000 slices (ARP, ICMP, UDP, TCP). Application notes are being written that discuss its operation, testing and performance.

We now offer DoD-sponsored security devices for FPGAs in the form of a Physically Uncloneable Function (PUF). Each PUF is identical to others, but because of subtle process variations the output of each is independent. A unique n-bit identifier results by replicating n PUFs on the FPGA. Each PUF is extremely compact since it fits in a single CLB.

Each FPGA will have a unique PUF signature, allowing a FPGA to be uniquely identified and distinguished from other "identical" FPGAs.

A PUF can be also be used for traditional challenge-response queries. In addition a PUF can form a seed for public-private key infrastructure, where the private key never leaves the FPGA.