Mobius-generated HDL is vendor and target neutral, enabling implementation using any FPGA vendors products or as an ASIC. 

Synopsys Professional Services are currently performing synthesis, layout and verification of a Mobius2-generated clockless design. 

Camgian is a partner to Codetronix for the development of asynchronous null convention logic (NCL)  circuits. Clockless NCL circuits have several advantages including:

• no clock, so lower power
• no synchronous switching activity, so lower EMI
• handshaking using completion detection, so insensitive to process, voltage, and temperature (PVT) changes

Mobius is a perfect frontend to Xilinx ISE and EDK tools. 

Mobius is a tiny, multi-threaded, hierarchical language that can be compiled to either hw or sw. The Mobius compilers generate synthesizeable Verilog and VHDL or ansiC. 

The Xilinx website has more information about the Xilinx ESL Initiative. 

XPS integration

MPSoc in XPS

The tool xpsupdate replicates microprocessor structures and signals for each specified sw target. As a result, it is trivial to create and build a MPSoC with Mobius and XPS.

Even better, it is trivial to change the sw or hw target of any Mobius procedure, enabling rapid design exploration of multiple processors & multiple hardware cores.

The Xilinx FSL and IBM Coreconnect PLB interfaces are supported as sw-sw and sw-hw communication fabrics.

Enhanced productivity

Users code their application in the Mobius language, and use the Mobius simulator to verify functionality. The Mobius simulator is a fast transaction level simulator that is typically 100x faster than HDL simulators. 

Once functionality is as expected, simply generate Verilog or VHDL. The generated HDL includes the testbench which makes it simple to verify that the HDL is functioning as expected.

Simply import the HDL into a Xilinx ISE or Xilinx EDK project, and click "generate bitstream". The Xilinx tools will use suitable defaults to synthesize, place & route and generate a downloadable bitstream. 

Fast Synthesis and PAR

Mobius follows Xilinx recommended HDL coding practices, enabling the Xilinx synthesizer to accurately infer a circuit from the Mobius-generated HDL. 

Mobius generates hierarchical circuits that exclusively use local control and local data wires. There are no global wires other than clock and reset signals. As a result, the circuits can be quickly synthesized and place & routed. No more long runs!

Excellent Quality of Results

Benchmarks show that the of Mobius-generated HDL using Xilinx tools on Xilinx targets consistently achieves quality of results similar to hand-designed HDL cores.

Using Mobius together with Xilinx enables:

• lower development costs with dramatically increased productivity
• increased quality of results using a correct-by-construction circuit
• quality of results similar to hand-designed HDL

AllianceCORE Partners

Codetronix is a member of the Xilinx Alliance Program.