Design Flow

Mobius is a front-end to your existing design flow making it easy to add Mobius to benefit from higher productivity, higher quality, and high performance.

1. The Mobius source and testbench is validated with the fast transaction level model Mobius simulator
2. The Mobius compilers generate HW (Verilog, VHDL) and/or SW (C with scheduler) 
   
3. The XPSupdate generates a new XPS project with the HW targets, SW targets and bridges (e.g. OPB, PLB, FSL)
4. The Xilinx Platform Studio tools generates a bitstream for the HW targets and elf files for each SW target.

FPGA and ASIC

The Mobius-generated HW and SW is correct-by-construction, so you can minimize low-level verification. Codetronix guarantees the quality of the generated output.

Mobius-generated HW and SW is target-independent and vendor-neutral. This means that you can synthesize the generated behavioral description on either a FPGA or ASIC target. 

Customers have successfully used Mobius together with Synopsys DC to implement ASICs.

Target-independent & Vendor-neutral

Mobius generates VHDL, Verilog and AnsiC that is independent of any particular target FPGA or vendor tools. Mobius has successfully been deployed with Xilinx, Altera, Atmel, Synplicity and Synopsys tools.

Portability

Quality of Results